Evolutionary Dynamic Allocation of Relocatable Modules onto Partially Damaged Xilinx FPGAs

Dynamically and partially reconfigurable FieldProgrammable Gate Arrays (FPGAs) open the doors for new more advanced fault-tolerance techniques. This technology permits indeed to adjust at runtime the architecture of the system in order to keep it fault-free at every time. We present a tailored Genetic Algorithm (GA) aimed at online searching a fault-tolerant architecture for the system in terms of the optimal placement for its modules. On the contrary to other works, we also address inter-module communication related issues and the constraints imposed by the special features of reconfigurable devices when doing the search. We report on the experiments conducted that our search algorithm reduces by 3 times the computational burden, being thus appropriate to be executed at runtime and leading to improve the Mean Time To Recovery (MTTR).